• DocumentCode
    847006
  • Title

    Class of undetectable stuck-open branches in CMOS memory elements

  • Author

    Rubio, A. ; Kajihara, S. ; Kinoshita, K.

  • Author_Institution
    Dept. of Phys., Balearic Islands Univ., Palma, Spain
  • Volume
    139
  • Issue
    4
  • fYear
    1992
  • fDate
    8/1/1992 12:00:00 AM
  • Firstpage
    503
  • Lastpage
    506
  • Abstract
    The authors consider a class of undetectable stuck-open faults in CMOS circuit branches and show that in basic static latch and flip-flop circuits some branches are of this class. Moreover, undetectable stuck-open faults in transistors reported in recent works pertain to this class. It is shown that, in the case of stuck-open faults in these branches, the static circuit becomes a dynamic one. Because most of the undetectable stuck-open faults in branches (or transistors) in sequential memory elements are of this class, a general approach for DFT (design for testability) for these faults is proposed, and examples of fully detectable circuits are presented
  • Keywords
    CMOS integrated circuits; fault location; flip-flops; integrated circuit testing; integrated logic circuits; logic design; logic testing; sequential circuits; CMOS circuit branches; CMOS memory elements; design for testability; flip-flop circuits; sequential memory elements; static latch circuits; stuck-open faults; transistors; undetectable stuck-open branches;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings G
  • Publisher
    iet
  • ISSN
    0956-3768
  • Type

    jour

  • Filename
    160076