DocumentCode :
848023
Title :
Architectures for exponentiation in GF(2m)
Author :
Scott, P. Andrew ; Simmons, Stanley J. ; Tavares, Stafford E. ; Peppard, Lloyd E.
Author_Institution :
Dept. of Electr. Eng., Queen´´s Univ., Kingston, Ont., Canada
Volume :
6
Issue :
3
fYear :
1988
fDate :
4/1/1988 12:00:00 AM
Firstpage :
578
Lastpage :
585
Abstract :
Several VLSI architectures for performing exponentiation in GF(2 m) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2ei power, O⩽im-1, are precomputed and stored so that the intermediate product terms can be calculated in a parallel fashion. For the two approaches, both synchronous and asynchronous implementations are presented using standard and normal bases. The discussion emphasizes the design and performance tradeoffs incurred in developing such architectures
Keywords :
VLSI; codes; digital arithmetic; encoding; Galois fields; VLSI architectures; asynchronous implementations; exponentiation; finite fields; intermediate products; normal bases; standard base; synchronous implementation; Application software; Arithmetic; Computer architecture; Cryptography; Digital signal processing; Error correction codes; Galois fields; Polynomials; Silicon; Very large scale integration;
fLanguage :
English
Journal_Title :
Selected Areas in Communications, IEEE Journal on
Publisher :
ieee
ISSN :
0733-8716
Type :
jour
DOI :
10.1109/49.1927
Filename :
1927
Link To Document :
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