DocumentCode
84868
Title
On Refining Row-Based Detailed Placement for Triple Patterning Lithography
Author
Hsi-An Chien ; Ye-Hong Chen ; Szu-Yuan Han ; Hsiu-Yu Lai ; Ting-Chi Wang
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
34
Issue
5
fYear
2015
fDate
May-15
Firstpage
778
Lastpage
793
Abstract
In this paper, we study row-based detailed placement refinement for triple patterning lithography (TPL), which asks to find a refined detailed placement solution as well as a valid TPL layout decomposition under the objective of minimizing the number of stitches and the half-perimeter wirelength. Our problem does not have precoloring solutions of cells as the input, and it allows using techniques, including white space insertion, cell flipping, adjacent-cell swapping, and vertical cell movement, to optimize the solution quality. We first present (resource-constrained) shortest-path-based algorithms for several TPL-aware single-row placement problems that allow or disallow perturbing a given cell ordering. Based on these algorithms, we then propose an approach to our TPL-aware detailed placement refinement problem, which first minimizes the number of stitches and then minimizes the wirelength. Finally, we report extensive experimental results to demonstrate the effectiveness and efficiency of our approach.
Keywords
decomposition; lithography; wires (electric); TPL layout decomposition; TPL-aware single-row placement problem; adjacent-cell swapping; cell flipping; half-perimeter wirelength; precoloring solution; refined row-based detailed placement refinement; resource-constrained shortest-path-based algorithm; stitch minimization; triple patterning lithography; vertical cell movement; white space insertion; Color; Electronic mail; Joining processes; Layout; Lithography; Rails; White spaces; Detailed Placement Refinement; Detailed placement refinement; Layout Decomposition; Triple Patterning Lithography; layout decomposition; triple patterning lithography (TPL);
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2015.2408253
Filename
7052395
Link To Document