Title :
Asynchronous circuit synthesis with Boolean satisfiability
Author :
Gu, Jun ; Puri, Ruchir
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
fDate :
8/1/1995 12:00:00 AM
Abstract :
Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous circuits is a difficult and error-prone task. An adequate synthesis method will significantly simplify the design and reduce errors. In this paper, we present a general and efficient partitioning approach to the synthesis of asynchronous circuits from general Signal Transition Graph (STG) specifications. The method partitions a large signal transition graph into smaller and manageable subgraphs which significantly reduces the complexity of asynchronous circuit synthesis. Experimental results of our partitioning approach with large number of practical industrial asynchronous circuit benchmarks are presented. They show that, compared to the existing asynchronous circuit synthesis techniques, this partitioning approach achieves many orders of magnitude of performance improvements in terms of computing time, in addition to the reduced circuit implementation area. This lends itself well to practical asynchronous circuit synthesis from general STG specifications
Keywords :
Boolean functions; asynchronous circuits; circuit CAD; logic CAD; logic partitioning; signal flow graphs; Boolean satisfiability; asynchronous circuit synthesis; circuit benchmarks; circuit implementation area; computing time; partitioning approach; real time applications; signal transition graph; subgraphs; Application software; Asynchronous circuits; Circuit synthesis; Clocks; Computer errors; Digital communication; Integrated circuit synthesis; Real time systems; Signal design; Signal synthesis;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on