DocumentCode
849697
Title
Masking of unknown output values during output response compression by using comparison units
Author
Pomeranz, Irith ; Kundu, Sandip ; Reddy, Sudhakar M.
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
53
Issue
1
fYear
2004
fDate
1/1/2004 12:00:00 AM
Firstpage
83
Lastpage
89
Abstract
A circuit may produce unknown output values during simulation of a test set, e.g., due to an unknown initial state or due to the existence of tristate elements. Unknown output values in the output response of a circuit make it impossible to determine a single unique signature for the fault-free circuit when built-in self-test is used for testing the circuit. We consider the problem of synthesizing a logic block that replaces unknown output values in the output response of a circuit with a known constant. The logic block is constructed from building blocks called comparison units. The synthesis procedure ensures that the built-in self-test scheme will be able to detect all the faults detectable by the test set applied to the circuit while allowing a single unique signature to be computed. Two variations of the synthesis procedure are considered, a two-dimensional version suitable for synchronous sequential circuits without scan and for scan circuits with multiple scan chains and a one-dimensional version suitable for scan circuits with a single scan chain.
Keywords
automatic test pattern generation; built-in self test; fault simulation; sequential circuits; built-in self test; fault free circuit; output response compression; scan design; synchronous sequential circuit; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Sequential circuits;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2004.1255794
Filename
1255794
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