Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation

Systematic synthesis of digital signal processing (DSP) data format converter architectures using the minimum number of registers is addressed. Systematic lifetime analysis is used to calculate the minimum number of registers needed for the converter. A novel forward-backward register allocation technique is proposed for the synthesis of the converter; this allocation technique requires less area for the implementation of control circuits than a simpler forward-circulate allocation scheme. Furthermore, the forward-backward allocation scheme guarantees completion and sustains the interframe pipelining rate, whereas the forward-circulate scheme does not guarantee completion of the allocation. Examples of data format converters studied include matrix transposers, and a general (m, d₁)→(n, d₂)[w ] converter, which processes m words and d₁ bits per word in one input cycle and outputs n words and d₂ bits per word in each output cycle