• DocumentCode
    85052
  • Title

    Ultra-energy-efficient CMOS/magnetic nonvolatile flip-flop based on spin-orbit torque device

  • Author

    Jabeur, Kotb ; Di Pendina, G. ; Prenat, G.

  • Author_Institution
    INAC-SPINTEC, Univ. Grenoble Alpes, Grenoble, France
  • Volume
    50
  • Issue
    8
  • fYear
    2014
  • fDate
    April 10 2014
  • Firstpage
    585
  • Lastpage
    587
  • Abstract
    The spin-orbit-torque magnetic tunnel junction (SOT-MTJ) is a promising device for data storage. Most of the issues encountered with scalable spin transfer-torque (STT) devices are visibly moved. Thanks to a three-terminal architecture, the reliability is increased by separating the read and the write paths. Furthermore, SOT-induced magnetisation switching can be very fast, thanks to a low-resistive writing path. The writing operation is symmetrical. Thus, it requires the same current density to switch between the parallel and antiparallel states. All these advantages make the SOT-MTJ device an ultimate candidate for introducing non-volatility in ultra-fast and power-efficient integrated circuits. A mixed CMOS/magnetic non-volatile flip-flop (NVFF) is described. The proposed architecture offers the possibility to use the usual CMOS flip-flop functionality with possible magnetic data store and restore operations while keeping non-volatility when the circuit is powered off. With a 135 nm dimension, the SOT-MTJ-based NVFF demonstrated a very high switching with a 5× decrease in terms of writing energy/bit when compared with an STT device.
  • Keywords
    CMOS logic circuits; flip-flops; integrated circuit reliability; magnetic logic; magnetic storage; magnetoelectronics; power integrated circuits; CMOS flip-flop functionality; NVFF; SOT-MTJ; SOT-induced magnetisation switching; STT devices; antiparallel states; data storage; low-resistive writing path; magnetic data storage; parallel states; power-efficient integrated circuits; reliability; size 135 nm; spin-orbit torque device; spin-orbit-torque magnetic tunnel junction; three-terminal architecture; ultra-energy-efficient CMOS-magnetic nonvolatile flip-flop;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2014.0372
  • Filename
    6802143