Calibration of sampling clock skew in SHA-less pipeline ADCs

A gradient-based algorithm to adaptively calibrate sampling clock skew in sample-and-hold amplifier (SHA)-less pipeline analogue-to-digital converters (ADCs) is presented. It follows that the power consumption of pipeline ADCs can be substantially reduced at the architecture level by employing the SHA-less multi-bit-per-stage architecture and remedying the resulting sampling clock skew problem with calibration.