DocumentCode
851967
Title
High Speed Processor for FASTBUS
Author
Campbell, M. ; Blatt, S. ; Kasha, H. ; Schmidt, M. ; Fuhrmann, J. ; Larsen, R. ; Leipuner, L. ; Makowiecki, D. ; Morse, W. ; Rudolf, T. ; Sims, W. ; Zhaungzi, W.
Author_Institution
Yale University, New Haven, Connecticut 06520
Volume
28
Issue
1
fYear
1981
Firstpage
369
Lastpage
371
Abstract
This paper describes a processor designed to operate at a speed compatible with fastbus. It has been used in an experiment at the AGS in Brookhaven National Laboratory. Its function was to read data from various fastbus modules and store it in a buffer where it could later be read and further processed by a slower host computer. The data was formatted so that the host computer could more easily process it. The processor also made decisions based on the validity of the data and rejected bad events. The ratio of the number of triggers to the number of accepted events was about 20 to 1.
Keywords
Buffer storage; Clocks; Coupling circuits; Data handling; Fastbus; Laboratories; Logic circuits; Process design; Registers; Testing;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.1981.4331199
Filename
4331199
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