DocumentCode
852397
Title
New intra-gate-offset high-voltage thin-film transistor with misalignment immunity
Author
Huang, T.Y. ; Lewis, A.G. ; Wu, I.-W. ; Chiang, A. ; Bruce, R.H.
Author_Institution
Xerox Palo Alto Res. Centre, CA, USA
Volume
25
Issue
8
fYear
1989
fDate
4/13/1989 12:00:00 AM
Firstpage
544
Lastpage
545
Abstract
A new high-voltage thin-film transistor (HVTFT) which, for the first time, eliminates misalignment errors in the drain offset length is described. Unlike previous HVTFTs where the drain offset is determined by the alignment of two masking layers, it is set in the new device by the separation of two gates defined with the same mask, and is therefore immune to alignment errors. The new intra-gate-offset (ITGO) scheme introduces no extra processing compared to conventional HVTFTs, and improves device uniformity and reproducibility, allowing a relaxed alignment tolerance on the normally critical n+ implant mask.
Keywords
power transistors; thin film transistors; TFT; device uniformity improvement; drain offset length; high-voltage; intra-gate-offset; misalignment error elimination; misalignment immunity; n + implant mask; thin-film transistor;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19890372
Filename
46156
Link To Document