Simulation Study of the Selectively Implanted Deep-N-Well for PMOS SET Mitigation

Author

He Yibai ; Chen Shuming

Author_Institution

Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China

Volume

14

Issue

1

fYear

2014

fDate

Mar-14

Firstpage

99

Lastpage

103

Abstract

In this paper, a novel well structure for PMOS single-event transient (SET) mitigation is studied by way of technology computer-aided design (TCAD) numerical simulations. Based on a 90-nm CMOS technology, the simulation results show that the proposed selectively implanted deep-N-well (SIDNW) can significantly reduce the SET pulsewidth without area, power, and performance overheads, when compared with the conventional dual-well process. A comparison is also made with the triple-well process.

Keywords

CAD; CMOS integrated circuits; MOSFET; numerical analysis; radiation hardening (electronics); CMOS technology; PMOS SET mitigation; PMOS single-event transient; SIDNW; TCAD; computer-aided design; numerical simulations; selectively implanted deep-N-well; selectively implanted deep-n-well; size 90 nm; Doping; Electric potential; Inverters; MOS devices; Semiconductor process modeling; Solid modeling; Three-dimensional displays; Deep-N-well; parasitic bipolar amplification; radiation hardened by design (RHBD); single event; single-event transient (SET);

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2013.2290032

Filename

6657755