Efficient construction of aliasing-free compaction circuitry

Parallel testing of cores can reduce SOC test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize the required test bandwidth at the core outputs. Our proposed space and time compaction methodology guarantees a single-bit bandwidth, enabling the test of cores through the allocation of fewer chip pin-outs. In this way, our scheme maximizes parallelism among core tests