An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution

This paper presents a clock-less 8b ADC in 130 nm CMOS technology, which uses signal-dependent sampling rate and adaptive resolution through a time-varying comparison window, for applications with sparse input signals. Input-dependent dynamic bias is used to reduce comparator delay dispersion, thus helping to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54 dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20 kHz bandwidth with 3-9 μW power from a 0.8 V supply.