A two-chip interface for a MEMS accelerometer

Author

Kajita, Tetsuya ; Moon, Un-Ku ; Temes, Gábor C.

Author_Institution

Res. & Dev. Headquarters, Yamatake Corp., Kanagawa, Japan

Volume

51

Issue

4

fYear

2002

fDate

8/1/2002 12:00:00 AM

Firstpage

853

Lastpage

858

Abstract

A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is proposed. This scheme functions even with large parasitic capacitances between the sensor and the interface circuit. The op-amp noise is first-order shaped. Dithering circuit is also implemented on the chip, fabricated in an 1.6-μm CMOS process.

Keywords

CMOS analogue integrated circuits; accelerometers; capacitive sensors; delta-sigma modulation; force feedback; integrating circuits; microsensors; CMOS process; MEMS accelerometer; charge noise; cross-coupled correlated double sampling integrator; delta-sigma modulator; dithering; first-order shaped; large parasitic capacitances; op-amp noise; signal-to-noise ratio; third-order noise-shaping interface circuit; two-chip implementation; Accelerometers; CMOS process; Capacitive sensors; Circuit noise; Micromechanical devices; Noise shaping; Operational amplifiers; Parasitic capacitance; Signal sampling; Signal to noise ratio;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/TIM.2002.803508

Filename

1044774