Area-efficient and self-biased capacitor multiplier for on-chip loop filter

A self-biased capacitor multiplier is proposed to reduce the area of a large integrating capacitor in loop filters. A prototype Sigma-Delta fractional-N frequency synthesiser including the capacitor multiplier is fabricated with a 0.35 mum BiCMOS process. The designed capacitor multiplier makes capacitance of 2.72 nF from an on-chip capacitor of 170 pF with current consumption of 240 muA at 2.8 V. The frequency synthesiser demonstrates the in-band phase noise of -79 dBc/Hz at 5 kHz offset