DocumentCode
856833
Title
On RC line delays and scaling in VLSI systems
Author
Svensson, Christer ; Afghahi, M.
Author_Institution
Linkoping Univ.
Volume
24
Issue
9
fYear
1988
fDate
4/28/1988 12:00:00 AM
Firstpage
562
Lastpage
563
Abstract
Proposes that a special interconnection metal layer is introduced into the VLSI process and used for global clock distribution and communication. By this method the interconnection delay will not be a limiting factor for the speed of synchronous circuits in CMOS down to 0.3 μm feature sizes and up to 20 mm chip sizes
Keywords
CMOS integrated circuits; VLSI; clocks; 0.3 micron; CMOS; VLSI systems; global clock distribution; interconnection delay; interconnection metal layer; scaling; synchronous circuits;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
Filename
19571
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