DocumentCode
857481
Title
CMOS delay time model based on weighted peak current
Author
Kim, Ki Hyun ; Park, S.B.
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul
Volume
24
Issue
18
fYear
1988
fDate
9/1/1988 12:00:00 AM
Firstpage
1128
Lastpage
1129
Abstract
The authors propose a new CMOS delay time model with the configuration ratio, the input slope and the load condition taken into account. This model is based on the optimally weighted switching peak current. The delay equations are computationally effective and the error is typically within 10% of SPICE results
Keywords
CMOS integrated circuits; delays; integrated logic circuits; semiconductor device models; CMOS; MOS logic circuits; configuration ratio; delay equations; delay time model; input slope; load condition; optimally weighted switching peak current; timing analysis; weighted peak current;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
Filename
19585
Link To Document