DocumentCode :
857616
Title :
Latent effects due to ESD in CMOS integrated circuits: review and experiments
Author :
Greason, William D. ; Kucerovsky, Zdenec ; Chum, Kenneth W K
Author_Institution :
Dept. of Electr. Eng., Univ. of Western Ontario, London, Ont., Canada
Volume :
29
Issue :
1
fYear :
1993
Firstpage :
88
Lastpage :
97
Abstract :
A review of the current information published on the subject of EOS/ESD latent failures is presented. In order to gain a better understanding of the phenomena involved in the input protection networks of CMOS integrated circuits, measurements were performed on both commercially available integrated circuits and a set of custom designed and fabricated devices. The tests investigated the effects of electrical stress, thermal shock, exposure to ultraviolet light, and thermal annealing. The results demonstrate the presence of latent failures in CMOS integrated circuits following exposure to ESD. The cumulative effect of repeated discharge can be partially alleviated using thermal annealing or exposure to light. A charge injection model is proposed to interpret the results
Keywords :
CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit testing; CMOS integrated circuits; ESD; IC testing; UV light exposure; charge injection model; commercially available devices; custom designed devices; custom fabricated devices; electrical stress; input protection networks; latent failures; thermal annealing; thermal shock; ultraviolet light; Annealing; CMOS integrated circuits; Earth Observing System; Electrostatic discharge; Gain measurement; Integrated circuit measurements; Performance evaluation; Performance gain; Protection; Thermal stresses;
fLanguage :
English
Journal_Title :
Industry Applications, IEEE Transactions on
Publisher :
ieee
ISSN :
0093-9994
Type :
jour
DOI :
10.1109/28.195893
Filename :
195893
Link To Document :
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