Title :
Analysis of a half-rate bang-bang phase-locked-loop
Author :
Ramezani, Mehrdad ; Andre, C. ; Salama, T.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fDate :
7/1/2002 12:00:00 AM
Abstract :
This brief presents the timing analysis of a half-rate phaselocked loop (PLL) with a bang-bang phase detector. The lock-in behavior of the PLL is discussed and parameters such as jitter, lock-in frequency range, and lock-in time are calculated. Behavioral simulation is used to validate the analytical results with particular emphasis on the PLL lock-in behavior.
Keywords :
bang-bang control; circuit simulation; phase detectors; phase locked loops; synchronisation; timing; timing jitter; PLL lock-in behavior; Simulink simulation; bang-bang phase detector; behavioral simulation; clock recovery; data recovery; half-rate bang-bang phase-locked-loop; jitter; lock-in frequency range; lock-in time; timing analysis; Analytical models; Circuits; Clocks; Frequency synchronization; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Signal generators; Voltage-controlled oscillators;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
DOI :
10.1109/TCSII.2002.805020
