DocumentCode
860198
Title
Technique for compensation of errors in analogue multipliers
Author
Cichocki, Andrzej ; Unbehauen, R.
Author_Institution
Warsaw Tech. Univ., Poland
Volume
25
Issue
5
fYear
1989
fDate
3/2/1989 12:00:00 AM
Firstpage
305
Lastpage
307
Abstract
A new method for significantly reducing the effect of nonlinear errors on the performance of an analogue multiplier is presented. The method is especially well suited for switched-capacitor devices where time-shared (multiplexing) techniques can be easily employed. However, the method is quite general in nature and can be applied to any type of analogue integrated multiplier. The effectiveness of the technique has been checked through extensive simulation studies.
Keywords
analogue circuits; linear integrated circuits; multiplying circuits; analogue multipliers; compensation; errors; integrated multiplier; nonlinear errors; simulation studies; switched-capacitor devices;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19890213
Filename
19731
Link To Document