Title :
Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders
Author :
Mukhanov, O.A. ; Kirichenko, A.F.
Author_Institution :
Hypres Inc., Elmsford, NY, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
We have designed a Decimation-in-Time (DIT) radix 2 butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit word-length employs only 3400 junctions, occupies an area of 3.8/spl times/2.0 mm/sup 2/, and dissipates less than 1.1 mW power. The multiplier is implemented using the unique RSFQ bit-clock-pipelined schema. We have successfully tested a library of serial multiply-add elements: the 8-bit multiplier at 6.3 GHz and adders with dc bias margin /spl plusmn/20%. Finally, we have demonstrated full operation of the radix 2 butterfly chip with 5-bit word length.<>
Keywords :
adders; data flow computing; digital arithmetic; fast Fourier transforms; hypercube networks; integrated circuit layout; multiplying circuits; pipeline arithmetic; superconducting logic circuits; 1.1 mW; 16 bit; 32 bit; 32-point fast Fourier transform; 5 bit; 6.3 GHz; 8 bit; DC bias margin; RSFQ bit-clock-pipelined schema; carry-save serial adders; decimation-in-time radix 2 butterfly integrated circuit; high speed test; multiplier layout; parallel data flow architecture; power dissipation; serial RSFQ multiplier-adders; serial multipliers; Adders; Circuit testing; Clocks; Fast Fourier transforms; Nuclear physics; Radio frequency; Samarium; Software libraries; Superconductivity; Throughput;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
