Row-column parallel turbo decoding of product codes

A row-column parallel architecture of a turbo decoder dedicated to product codes is presented. This architecture enables simultaneous decoding of the row and the column of a block. The performance of the proposed row-column parallel turbo decoder is similar to that of a conventional turbo decoder. However, this new architecture reduces the decoding latency by a factor of two. Moreover, the memory necessary for the block reconstruction between row decoding and column decoding is removed.