A new design approach for High-T/sub c/ based RSFQ logic

Author

Kaplunenko, V.K. ; Ivanov, Z.G. ; Bogdanov, A. ; Stepantsov, E.A. ; Claeson, T. ; Holst, T. ; Sun, Z.J. ; Kromann, R. ; Shen, Y.Q. ; Vase, P. ; Freitoft, T. ; Wikborg, E.

Author_Institution

Dept. of Phys., Chalmers Univ. of Technol., Goteborg, Sweden

Volume

5

Issue

2

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

2835

Lastpage

2838

Abstract

We suggest a new design of Rapid Single Flux Quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. The small inductances of about 10 pH, that are obligatory for the RSFQ applications, are formed as narrow slits with width comparable to the London penetration depth (/spl cong/0.15 /spl mu/m). The design allows us to decrease the geometric size of the RSFQ cell and can be applied to low-T/sub c/ circuits as well. Test circuits have been implemented using YBaCuO grain boundary junctions on assymmetric 32/spl deg/Y-ZrO/sub 2/ bi-crystals to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 pm slit was determined to be 0.7pH//spl mu/m. We present a new design and a computer simulation of a flip-flop circuit based on these inductance measurements. To realize these circuits experimentally one needs at least two grain boundaries, separated by a distance of 10 to l5 /spl mu/m, or to use bi-epitaxial or step-edge junction technology.<>

Keywords

barium compounds; flip-flops; grain boundaries; high-temperature superconductors; inductance; penetration depth (superconductivity); superconducting logic circuits; yttrium compounds; 0.4 micron; 10 to 15 micron; London penetration depth; RSFQ logic; YBaCuO grain boundary junctions; YBaCuO-ZrO/sub 2/; ZrO/sub 2/; bi-epitaxial technology; flip-flop circuit; geometric size; inductances; mutual inductance; rapid single flux quantum; single superconducting layer; slit inductance per unit length; step-edge junction technology; Circuit testing; Computer simulation; Flip-flops; Grain boundaries; Inductance measurement; Length measurement; Logic circuits; Superconducting epitaxial layers; Superconducting logic circuits; Yttrium barium copper oxide;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.403182

Filename

403182