DocumentCode :
862275
Title :
Optimal wire-sizing function under the Elmore delay model with bounded wire sizes
Author :
Lee, Yu-Min ; Chen, Charlie Chung-Ping ; Wong, D.F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Volume :
49
Issue :
11
fYear :
2002
fDate :
11/1/2002 12:00:00 AM
Firstpage :
1671
Lastpage :
1677
Abstract :
In this brief, we develop the optimal wire-sizing functions under the Elmore delay model with bounded wire sizes. Given a wire segment of length L, let f(x) be the width of the wire at position x, 0≤x≤L. We show that the optimal wire-sizing function that minimizes the Elmore delay through the wire is f(x)=ae-bx, where a>0 and b>0 are constants that can be computed in O(1) time. In the case where lower bound (L>0) and upper bound (U>0) of the wire widths are given, we show that the optimal wire-sizing function f(x) is a truncated version of ae-bx that can also be determined in O(1) time. Our wire-sizing formula can be iteratively applied to optimally size the wire segments in a routing tree.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; network routing; wiring; Elmore delay model; VLSI; bounded wire sizes; deep submicron designs; interconnect delay; lower bound; optimal wire-sizing function; routing tree; upper bound; wire segment; wire widths; Capacitance; Circuit optimization; Delay effects; Integrated circuit interconnections; Large scale integration; Routing; Runtime; Upper bound; Very large scale integration; Wire;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7122
Type :
jour
DOI :
10.1109/TCSI.2002.804598
Filename :
1046839
Link To Document :
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