A two stage inverter large scale static VAR compensator with minimum filtering requirements

The authors present the description, steady-state modeling, and filter design of a double-inverter PWM (pulse-width-modulated) solid-state synchronous condenser (SSSC) for reactive power compensation. The proposed scheme integrates the advantages of PWM selective harmonic elimination modulation (SHEM) and harmonic cancellation by transformer connection (HCTC) to minimize the filtering requirements. The key feature of the proposed double-inverter SSSC system is the low-switching frequency of the PWM pattern, which allows the utilization of high-power GTO (gate turn-off) thyristors (f _sw,max=420 Hz). A series of PWM switching patterns in the low-switching frequency range that is most suitable for high-power GTO thyristors is presented. The performances of the SSSC for these PWM patterns are compared. Other figures of merit for the system, such as filter design and system derating, are discussed. The steady-state waveforms of the compensator current for single- and double-inverter SSSC systems are compared