Bit Error Rate Minimizing Channel Shortening Equalizers for Cyclic Prefixed Systems

Cyclic prefixed communications, such as multicarrier communications, first became widely used in the context of digital subscriber lines (DSL). In DSL, bit loading is allowed at the transmitter, and the performance metric is the bit rate that can be provided without exceeding a given bit error rate (BER). Wireless cyclic prefixed systems are now becoming increasingly popular, and in such systems the appropriate performance metric is the BER for a given bit loading at the transmitter. Cyclic prefixed systems perform well in the presence of multipath, provided that the channel delay spread is shorter than the guard interval between transmitted blocks. If this condition is not met, a channel shortening equalizer can be used to shorten the channel to the desired length. Previous work on channel shortening has largely been in the context of DSL, thus it has focused on maximizing the bit rate. In this paper, we propose a channel shortener that attempts to directly minimize the BER for a multiple-input multiple-output channel model. We simulate the performance of the resulting channel shortener and compare it to existing designs and the matched filter bound