Title :
An asynchronous architecture for modeling intersegmental neural communication
Author :
Patel, Girish N. ; Reid, Michael S. ; Schimmel, David E. ; DeWeerth, Stephen P.
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented; data from this system are presented.
Keywords :
VLSI; asynchronous circuits; integrated circuit design; logic design; neural nets; address-event representation; asynchronous VLSI architecture; asynchronous circuits; burst envelopes; communicating hardware processes; communications network; data transmission; intersegmental neural communication modeling; intersegmental synaptic connectivity; multichip communication; neuromorphic protocol; oscillatory patterns; segmented biological systems; silicon neuron; spiking envelopes; Asynchronous circuits; Biological system modeling; Biological systems; Circuit synthesis; Communication networks; Data communication; Network synthesis; Neuromorphics; Protocols; Very large scale integration; Address event representation (AER); VLSI architecture; asynchronous circuits; central pattern generator (CPG); neurobiological modeling; neuromorphic engineering; silicon neuron;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2005.863762
