A 10-Bit 800-MHz 19-mW CMOS ADC

Author

Chiang, Shiuh-Hua Wood ; Hyuk Sun ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Irvine, Irvine, CA, USA

Volume

49

Issue

4

fYear

2014

fDate

Apr-14

Firstpage

935

Lastpage

949

Abstract

A pipelined ADC employs charge-steering op amps to relax the trade-offs among speed, noise, and power consumption. Such op amps afford a fourfold increase in speed and a twofold reduction in noise for a given power consumption and voltage gain. Applying full-rate nonlinearity and gain error calibration, a prototype realized in 65-nm CMOS technology exhibits a Nyquist SNDR of 52.2 dB and draws 19 mW at 800 MHz. The ADC also demonstrates a new histogram-based background calibration technique.

Keywords

CMOS integrated circuits; UHF integrated circuits; analogue-digital conversion; calibration; CMOS technology; Nyquist SNDR; analog-to-digital converters; charge-steering op amps; frequency 800 MHz; full-rate nonlinearity; gain error calibration; histogram-based background calibration technique; noise twofold reduction; pipelined ADC; power 19 mW; power consumption; voltage gain; word length 10 bit; Calibration; Capacitors; Clocks; Mathematical model; Noise; Operational amplifiers; Switches; Charge-steering; digital calibration; dynamic op amp; nonlinearity correction; pipelined ADCs;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2300199

Filename

6730708