DocumentCode
865740
Title
Thread partitioning and value prediction for exploiting speculative thread-level parallelism
Author
Marcuello, Pedro ; González, Antonio ; Tubella, Jordi
Author_Institution
Dept. d´´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
Volume
53
Issue
2
fYear
2004
fDate
2/1/2004 12:00:00 AM
Firstpage
114
Lastpage
125
Abstract
Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model strongly depends on the performance of the control and data speculation techniques. Several hardware-based schemes for partitioning the program into speculative threads are analyzed and evaluated. In general, we find that spawning threads associated to loop iterations is the most effective technique. We also show that value prediction is critical for the performance of all of the spawning policies. Thus, a new value predictor, the increment predictor, is proposed. This predictor is specially oriented for this kind of architecture and clearly outperforms the adapted versions of conventional value predictors such as the last value, the stride, and the context-based, especially for small-sized history tables.
Keywords
iterative methods; multi-threading; parallel architectures; parallelising compilers; prediction theory; program control structures; program slicing; branch prediction; clustered architecture; data speculation technique; history table; increment predictor; speculative thread-level parallelism; thread partitioning; thread spawning policies; value prediction; Accuracy; Application software; Computer Society; History; Microarchitecture; Parallel processing; Processor scheduling; Runtime; Size control; Yarn;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2004.1261823
Filename
1261823
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