• DocumentCode
    86602
  • Title

    Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction

  • Author

    Joshi, Rajiv V. ; Keunwoo Kim ; Kanj, Rouwaida ; Bhoj, Ajay N. ; Ziegler, Matthew M. ; Oldiges, Phil ; Kerber, Pranita ; Wong, Robert ; Hook, Terence ; Saroop, Sudesh ; Radens, Carl ; Chun-Chen Yeh

  • Author_Institution
    IBM TJ Watson Labs., Yorktown Heights, NY, USA
  • Volume
    23
  • Issue
    3
  • fYear
    2015
  • fDate
    Mar-15
  • Firstpage
    534
  • Lastpage
    543
  • Abstract
    We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory (SRAM) design, overcomes this barrier by leveraging advanced physics-based 2-D (P2-D) devices with optimized meshes that are derived from 3-D FinFET models with tuned device parasitics. This enables physics-based simulation as well as physics-based variability input parameters. To improve accuracy, an embedded automated flow enables extraction of all external nodal parasitics, directly from a 3-D FinFET circuit layout representation. The circuits consisting of advanced P2-D devices are then back annotated with the nodal parasitics to enable fast and accurate SRAM dynamic margin mixed-mode simulations. Results demonstrate up to 200× speedup compared with traditional 3-D device simulations, and around five orders of magnitude wall clock time improvement on account of fast statistical methodologies, which are superior in comparison with traditional Monte Carlo analysis. This makes it feasible to supplant often inaccurate compact model-based simulations by true mixed-mode device simulations in statistical engines. The proposed physics-based methodology is also shown to corroborate well with hardware measurements.
  • Keywords
    MOSFET; SRAM chips; mixed analogue-digital integrated circuits; semiconductor device models; statistical analysis; 3D FinFET circuit layout representation; 3D FinFET models; 3D technology computer aided design models; FinFET-trigate static random access memory design; SRAM dynamic margin mixed-mode simulations; embedded automated flow enables extraction; memory yield prediction; physics-based mixed-mode statistical simulation; statistical engines; Capacitance; Computational modeling; Delays; FinFETs; Integrated circuit modeling; Semiconductor process modeling; Solid modeling; Capacitance; FinFET; Technology Computer Aided Design (TCAD).; fast statistical sampling; physics-based models; static noise margin (SNM); static random access memory (SRAM); technology Computer Aided Design (TCAD);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2313815
  • Filename
    6802410