POD: A 3D-Integrated Broad-Purpose Acceleration Layer

Author

Woo, Dong Hyuk ; Lee, Hsien-Hsin S. ; Fryman, Joshua B. ; Knies, Allan D. ; Eng, Marsha

Author_Institution

Georgia Inst. of Technol., Atlanta, GA

Volume

28

Issue

4

fYear

2008

Firstpage

28

Lastpage

40

Abstract

To build a future many-core processor, industry must address the challenges of energy consumption and performance scalability. A 3D-integrated broad-purpose accelerator architecture called parallel-on-demand (POD) integrates a specialized SIMD-based die layer on top of a CISC superscalar processor to accelerate a variety of data-parallel applications. It also maintains binary compatibility and facilitates extensibility by virtualizing the acceleration capability.

Keywords

logic design; low-power electronics; microprocessor chips; parallel architectures; parallel machines; CISC superscalar processor; POD 3D-integrated broad-purpose accelerator architecture; SIMD-based die layer; acceleration capability virtualization; binary compatibility; data-parallel applications; energy consumption; many-core processor; parallel SIMD designs; parallel-on-demand architecture; performance scalability; Acceleration; Accelerator architectures; Application virtualization; Broadcasting; Energy consumption; Multicore processing; Packaging; Process design; Scalability; Transistors;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2008.58

Filename

4626816