SMTA: next-generation high-performance multi-threaded processor

Multi-threading is one of the methods of improving the performance of processors. In this paper, a super-multi-threaded processor is proposed. In the multi-threaded architecture, a thread dispatcher is constructed to manage the thread-level parallelism and instruction-level parallelism, and to build a communication unit to transfer the dependence data among the threads. Furthermore, the authors illustrate the control flow with a Petri net model, and simulate the proposed architecture using a trace-driven simulation tool suite. From the simulation results, the authors find that the proposed architecture achieves two goals: the individual thread slot in the proposed multi-threaded processor achieves more significant throughput gains than the DLX pipeline processor, and it minimises the cost of the expansion of multi-threaded processor systems.