DocumentCode
866339
Title
Using march tests to test SRAMs
Author
Van de Goor, Ad J.
Author_Institution
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Volume
10
Issue
1
fYear
1993
fDate
3/1/1993 12:00:00 AM
Firstpage
8
Lastpage
14
Abstract
A unified notation is presented for static random access memory (SRAM) fault models and fault tests for these models. The likelihood that the different types of faults will occur is demonstrated using inductive fault analysis and physical defect analysis. A set of march tests is discussed, together with methods to make composite tests for collections of fault tapes. Empirical results showing the fault coverage of the different test enable SRAM users to choose the fault models of interest as well as the test.<>
Keywords
SRAM chips; fault location; integrated circuit testing; integrated memory circuits; SRAMs; fault models; fault tests; inductive fault analysis; march tests; physical defect analysis; static random access memory; unified notation; Decoding; Iron; Logic arrays; Random access memory; Read-write memory; SRAM chips; Testing; Virtual manufacturing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.199799
Filename
199799
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