DocumentCode
869481
Title
An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch
Author
Nikoozadeh, Amin ; Murmann, Boris
Author_Institution
Dept. of Electr. Eng., Stanford Univ., CA
Volume
53
Issue
12
fYear
2006
Firstpage
1398
Lastpage
1402
Abstract
This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several tens of millivolts
Keywords
CMOS integrated circuits; comparators (circuits); network analysis; 0.18 micron; HSpice simulations; latch comparator analysis; load capacitor mismatch; Analytical models; Capacitance; Capacitors; Inverters; Latches; MOS devices; MOSFET circuits; Switches; Switching circuits; Threshold voltage; Capacitor mismatch; dynamic offset; latch;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2006.883204
Filename
4033159
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