Title :
DFT infrastructure for broadside two-pattern test of core-based SOCs
Author :
Xu, Qiang ; Nicolici, Nicola
Author_Institution :
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China
fDate :
4/1/2006 12:00:00 AM
Abstract :
Existing approaches for modular manufacturing test of core-based system-on-a-chip (SOC) devices do not provide any explicit mechanism for delivering two-pattern tests in the broadside mode, which is necessary to achieve reliable coverage of delay and stuck-open faults. Although wrapper input cells can be enhanced with two memory elements to address this problem, this incur a large test area overhead. This paper proposes a novel architecture for broadside two-pattern test of core-based SOCs without any loss in fault coverage and without increasing the size of the wrapper input cells. The proposed solution combines the dedicated bus-based test access mechanism and functional interconnects for test data transfer in order to provide full controllability of the wrapper input cells in the two consecutive clock cycles required by two-pattern testing. New algorithms for test access mechanism design and test scheduling are proposed and design trade-offs between test area and testing time are discussed using experimental results.
Keywords :
design for testability; integrated circuit design; logic testing; system-on-chip; DFT infrastructure; broadside two-pattern test; bus-based test access mechanism; clock cycles; core-based SOC; delays; modular manufacturing; stuck-open faults; system-on-a-chip; test access mechanism design; test scheduling; wrapper input cells; Algorithm design and analysis; Circuit faults; Circuit testing; Clocks; Delay; Logic circuits; Sequential analysis; System testing; System-on-a-chip; Timing; System-on-a-chip; embedded core delay test.;
Journal_Title :
Computers, IEEE Transactions on