Single-Event Tolerant Latch Using Cascode-Voltage Switch Logic Gates

Author

Casey, Megan C. ; Bhuva, Bharat L. ; Black, Jeff D. ; Massengill, Lloyd W. ; Amusan, Oluwole A. ; Witulski, Arthur F.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN

Volume

53

Issue

6

fYear

2006

Firstpage

3386

Lastpage

3391

Abstract

A new latch design using Cascode-Voltage Switch Logic gates is evaluated for single event (SE) environments. The latch design is based on the DICE latch design, but with CVSL gates. Calibrated 3D device models for an IBM 130 nm technology were used for mixed-mode simulations of the latch for SE evaluations. Simulation results show that the latch is immune to charge deposition on multiple nodes. The proposed design does require a 60% increase in area and double the power, but is faster than conventional DICE-based latch design

Keywords

CMOS logic circuits; circuit simulation; flip-flops; logic design; logic gates; radiation hardening (electronics); semiconductor device models; 3D device models; CMOS; cascode-voltage switch logic gates; charge deposition; conventional DICE-based latch design; digital circuits; mixed-mode simulations; radiation hardening; sequential circuits; single-event tolerant latch; Circuit simulation; Digital circuits; Feedback; Latches; Logic design; Logic devices; Logic gates; Radiation hardening; Single event transient; Switches; CMOS; digital circuits; radiation hardening; sequential circuits; single-event;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2006.884970

Filename

4033284