DocumentCode
871344
Title
A real-time industrial pattern classification system
Author
Khalaf, S. ; Zhu, Mingda ; Siy, P. ; Abdelguerfi, M.
Author_Institution
Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI
Volume
36
Issue
1
fYear
1989
fDate
2/1/1989 12:00:00 AM
Firstpage
84
Lastpage
85
Abstract
Using the partitioned matrix approach, a parallel hardware architecture for a parametric (Bayes) classifier is designed. The architecture consists of simple, regularly structured processing elements operating in parallel. As a result, the proposed design is suitable for VLSI implementation. A comparative analysis shows that the approach is more efficient and can significantly reduce the cost required for implementing the classifier, while maintaining high speed
Keywords
Bayes methods; computerised pattern recognition; matrix algebra; Bayes methods; VLSI; computerised pattern recognition; industrial pattern classification; parallel hardware architecture; partitioned matrix; Classification algorithms; Computer architecture; Costs; Hardware; Matrix decomposition; Pattern classification; Pattern recognition; Prototypes; Real time systems; Very large scale integration;
fLanguage
English
Journal_Title
Industrial Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0278-0046
Type
jour
DOI
10.1109/41.20350
Filename
20350
Link To Document