Title :
Pitfalls of hierarchical fault simulation
Author_Institution :
Intel Corp., Austin, TX, USA
Abstract :
Certain circuit structures, such as self-loop, asynchronous reset, and clock division, may not be visible in a hierarchical (mixed) simulation system. Since the simulator does not know about their existence, it cannot cope with them like it normally would in a flat circuit. If this leads to a logic-simulation problem, users can usually discover them easily during the validation process. However, if it only causes fault-simulation inaccuracy, it is hard to find the problem. In this paper, we show examples illustrating their existence. The examples negate an assumption that has been used in many papers on mixed-mode simulation. The examples have been abstracted from real industrial designs of microprocessors.
Keywords :
circuit testing; fault simulation; logic simulation; sequential circuits; asynchronous reset; circuit structures; clock division; fault simulation; flat circuit; logic-simulation problem; microprocessor designs; mixed-mode simulation; self-loop circuit; sequential circuit; sequential logic circuit testing; Circuit faults; Circuit simulation; Circuit testing; Clocks; Flip-flops; Logic testing; Microprocessors; Sequential analysis; Sequential circuits; System testing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.822099
