DocumentCode :
871420
Title :
XID: Don´t care identification of test patterns for combinational circuits
Author :
Miyase, Kohei ; Kajihara, Seiji
Author_Institution :
Graduate Sch. of Comput. Sci. & Syst. Eng., Kyusyu Inst. of Technol., Iizuka, Japan
Volume :
23
Issue :
2
fYear :
2004
Firstpage :
321
Lastpage :
326
Abstract :
Given a test set for stuck-at faults of a combinational circuit or a full-scan sequential circuit, some of the primary input values may be changed to the opposite logic values without losing fault coverage. We can regard such input values as don´t care (X). In this paper, we propose a method for identifying the X inputs of test vectors in a given test set. While there are many combinations of X inputs in the test set generally, the proposed method finds one including as many X inputs as possible, by using fault simulation and procedures similar to implication and justification of automatic test pattern generation (ATPG) algorithms. Experimental results for ISCAS benchmark circuits show that approximately 69% of the inputs of uncompacted test sets could be X on the average. Even for highly compacted test sets, the method found that approximately 48% of inputs are X.
Keywords :
automatic test pattern generation; combinational circuits; fault diagnosis; fault simulation; ATPG; XID; automatic test pattern generation; benchmark circuits; combinational circuits; don´t care identification; fault coverage; fault simulation; logic values; sequential circuit; stuck-at faults; test patterns; test relaxation; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Logic testing; Sequential analysis; Sequential circuits;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2003.822103
Filename :
1262469
Link To Document :
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