Current Status of Large Scale Integration Technology

The current status of large scale integration (LSI) technology is reviewed, with emphasis on developments made during the past year. Problem areas and solution approaches are emphasized, Four LSI technologies are considered as follows. 1) LSI bipolar chip technology (100 percent yield over chip area) reviews progress toward increasing the cornplexit y level on semiconductor chips. Conclusions of a Texas Instruments study of yie!d versus chip area are discussed, and a forecast is made of complexity levels for logic and memory. Several master-slice customization programs now under development in industry are reviewed. 2) LSI full-slice technology (discretionary wiring) is discussed for read-write and read-only memory of 1600 bits per slice and customized logic of 100 to 250 gates per slice. 3) LSI MOS technology is reviewed emphasizing progress in speed improvements and area reduction through development of four-phase ratioless circuitry. Technological factors which govern MOS speed are discussed. 4) LSI hybrid technology is briefly discussed. The paper concludes with a discussion of complexity versus cost, perfommce, and reliability for various LSI technologies. The problem of selecting an optimum LSI technology for a given application is discussed by consideration of several specific examples.