Inherent pattern jitter of STM-64 format signal and a reduction method

The inherent pattern jitter of the STM-64 format signal is found to be increased by the DC level fluctuation of incoming data and the output power variation of the timing tank in the section overhead bytes which become longer than the time constant of the timing tank. This pattern jitter is reported to be successfully suppressed by using an already proposed timing recovery circuit with a 1/2T differentiator, which operates as a pattern transformer.