DocumentCode :
874031
Title :
Address selection by combinatorial decoding of semiconductor memory arrays
Author :
Greene, F.S. ; Sander, W.B.
Volume :
4
Issue :
5
fYear :
1969
Firstpage :
295
Lastpage :
296
Abstract :
On-chip decoding for address selection is being designed into large- capacity semiconductor memory chips to reduce the number of off-chip interconnections. A combinatorial form of decoding is offered as an alternative to the usual straight binary or selection matrix form of decoding. Combinatorial decoding circuit complexity and pad reduction, and provides an easy method of selecting a redundant line on the chip. This form of decoding uses the (/SUB m//SUP n/) combinations of n bits taken m at a time, whereas the usual binary decoding uses 2/SUP n/ combinations. Because most systems are organized in binary form, a code conversion is required to use the combinatorial form of address decoding. Since the code conversion is equivalent to a level of decoding, there is only a small logic penalty to pay.
Keywords :
Code convertors; Decoding; Semiconductor storage devices; code convertors; decoding; semiconductor storage devices; Complexity theory; Decoding; Integrated circuit interconnections; Logic devices; MOSFETs; Semiconductor diodes; Semiconductor memory;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1969.1050021
Filename :
1050021
Link To Document :
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