A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC

This paper presents a new ADC architecture called partially active flash ADC. A 10 GS/s 6 b four-way time-interleaved ADC prototype in 65 nm CMOS demonstrated that this new ADC architecture offers better power efficiency than traditional ADC architectures in the ≥10 GS/s speed range. Various considerations towards high-speed ADC designs are discussed including a proposed source-follower based boot-strap track-and-hold circuit to reduce input kickback and improve the ADC bandwidth. Also discussed is the generation and skew calibration of the four-phase clocks for the interleaved channels to improve the ADC effective resolution at high input frequencies. By deriving the four-phase clocks from a Nyquist frequency input clock through pass gates, accurate timing skew calibration is achieved through a simple duty-cycle correction. Measured SNDR is 34.3 dB at low input frequencies and 32.0 dB at the Nyquist input frequency. The ADC including the input clock buffer consumes 83 mW with a FOM of 197 fJ/cs.