Title :
A new method for hierarchical compaction [VLSI]
Author :
Rülling, Wolfgang ; Schilz, Thomas
Author_Institution :
Fachhochschule Furtwangen, FB Ingenieur-Inf., Germany
fDate :
2/1/1993 12:00:00 AM
Abstract :
A framework for the compaction of hierarchically specified layout sketches is proposed. The main advantage of the method is that it maintains the layout hierarchy. Thus, the produced output has the same efficient representation as the input and further efficient processing of the layout becomes possible
Keywords :
VLSI; circuit layout CAD; integrated circuit technology; VLSI design; hierarchical compaction; layout hierarchy; Compaction; Minimization methods; Optimization methods; Very large scale integration; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
