Turning silicon on its edge [double gate CMOS/FinFET technology]

Author

Nowak, Edward J. ; Aller, Ingo ; Ludwig, Thomas ; Kim, Keunwoo ; Joshi, Rajiv V. ; Chuang, Ching-Te ; Bernstein, Kerry ; Puri, Ruchir

Author_Institution

Microelectron. Div., IBM, Essex Junction, VT, USA

Volume

20

Issue

1

fYear

2004

Firstpage

20

Lastpage

31

Abstract

Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

Keywords

CMOS integrated circuits; MOSFET; VLSI; dielectric thin films; low-power electronics; 180 nm; CMOS scaling; DGCMOS-FinFET; FinFET technology; double-gate CMOS devices; foundry-compatible process; gate dielectric barrier; high-performance VLSI; integrated CMOS circuits; low-power VLSI; CMOS process; CMOS technology; Circuits; Dielectrics; FinFETs; Fluctuations; Product design; Silicon; Turning; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/MCD.2004.1263404

Filename

1263404