The DASH prototype: Logic overhead and performance

Author

Lenoski, Daniel ; Laudon, James ; Joe, Truman ; Nakahira, David ; Stevens, Luis ; Gupta, O.P. ; Hennessy, John

Author_Institution

Comput. Syst. Lab., Stanford Univ., CA, USA

Volume

4

Issue

1

fYear

1993

fDate

1/1/1993 12:00:00 AM

Firstpage

41

Lastpage

61

Abstract

The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. The hardware overhead of directory-based cache coherence in a 48-processor is examined. The data show that the overhead is only about 10-15%, which appears to be a small cost for the ease of programming offered by coherent caches and the potential for higher performance. The performance of the system is discussed, and the speedups obtained by a variety of parallel applications running on the prototype are shown. Using a sophisticated hardware performance monitor, the effectiveness of coherent caches and the relationship between an application´s reference behavior and its speedup are characterized. The optimizations incorporated in the DASH protocol are evaluated in terms of their effectiveness on parallel applications and on atomic tests that stress the memory system

Keywords

buffer storage; parallel programming; performance evaluation; shared memory systems; storage management; DASH project; DASH protocol; atomic tests; coherent caches; directory-based cache coherence; hardware performance monitor; large-scale shared-memory multiprocessors; reference behavior; Costs; Hardware; Large-scale systems; Logic; Parallel architectures; Parallel programming; Protocols; Prototypes; Scalability; Software prototyping;

fLanguage

English

Journal_Title

Parallel and Distributed Systems, IEEE Transactions on

Publisher

ieee

ISSN

1045-9219

Type

jour

DOI

10.1109/71.205652

Filename

205652