• DocumentCode
    87644
  • Title

    Part II: Investigation of Subthreshold Swing in Line Tunnel FETs Using Bias Stress Measurements

  • Author

    Walke, Amey Mahadev ; Vandooren, A. ; Kaczer, Ben ; Verhulst, Anne S. ; Rooyackers, R. ; Simoen, Eddy ; Heyns, M.M. ; Rao, Valipe Ramgopal ; Groeseneken, Guido ; Collaert, Nadine ; Thean, Aaron Voon-Yew

  • Author_Institution
    Interuniv. Microelectron. Centre, Leuven, Belgium
  • Volume
    60
  • Issue
    12
  • fYear
    2013
  • fDate
    Dec. 2013
  • Firstpage
    4065
  • Lastpage
    4072
  • Abstract
    The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H+ species released from the Si/ SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs.
  • Keywords
    field effect transistors; passivation; stress effects; tunnelling; H+; Si-SiO2; TFET; bias stress measurement; bulk semiconductor trap density; interface state density; line tunnel FET; line tunnel field effect transistor; negative stress; passivation process; subthreshold swing; trap assisted tunneling; Charge pumps; Degradation; Dielectrics; Interface states; Logic gates; Silicon; Stress; Bias stress measurements; bulk traps; characterization; fabrication; interface traps; line tunnel field-effect transistors (TFET); subthreshold swing (SS) degradation; trap-assisted tunneling (TAT); tunnel FET (TFET);
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2013.2287253
  • Filename
    6658861