A New Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-Based FPGAs

Author

Sterpone, Luca ; Violante, Massimo

Author_Institution

Politec. di Torino, Turin

Volume

55

Issue

4

fYear

2008

Firstpage

2019

Lastpage

2027

Abstract

In this paper we present an analytical analysis of the fault masking capabilities of triple modular redundancy (TMR) hardening techniques in the presence of multiple cell upsets (MCUs) in the configuration memory of SRAM-based field-programmable gate arrays (FPGAs). The analytical method we developed allows an accurate study of the MCUs provoking domain crossing errors that defeat TMR. From our analysis we have found that most of the failures affect configurable logic block´s routing resources. The experimental analysis has been performed on two realistic case study circuits. Experimental results are presented and discussed showing in particular that 2-bits MCUs may corrupt TMR 2.6 orders of magnitude more than single cell upsets (SCUs).

Keywords

SRAM chips; fault diagnosis; fault tolerance; field programmable gate arrays; integrated circuit testing; radiation hardening (electronics); redundancy; MCU sensitiveness; SRAM-based FPGA; SRAM-based field-programmable gate arrays; STAR-MCU algorithm; TMR architectures; analytical method; configurable logic blocks routing resources; configuration memory; domain crossing errors; fault masking capabilities; fault tolerance; multiple cell upsets; triple modular redundancy hardening techniques; Algorithm design and analysis; Circuit faults; Costs; Field programmable gate arrays; Integrated circuit technology; Ionizing radiation; Logic; Random access memory; Redundancy; Routing; Analytical analysis; field-programmable gate array (FPGA); multiple cell upset; triple modular redundancy (TMR);

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2008.2001858

Filename

4636938