DocumentCode
878159
Title
Grounded load complementary FET circuits: Sceptre analysis
Author
Sakamoto, Hiroo ; Forbes, Leonard
Volume
8
Issue
4
fYear
1973
fDate
8/1/1973 12:00:00 AM
Firstpage
282
Lastpage
284
Abstract
The performance of grounded load complementary MOS circuits has been evaluated. It has been found that a very significant improvement in performance and reduction in circuit-area might be achieved by employing grounded load devices in portions of a system employing large-scale integrated CMOS circuits.
Keywords
Computer-aided circuit analysis; Field effect transistors; Large scale integration; Logic circuits; computer-aided circuit analysis; field effect transistors; large scale integration; logic circuits; Broadband amplifiers; Circuit analysis; Circuit simulation; Computational modeling; FET circuits; Integrated circuit modeling; Integrated circuit noise; Large scale integration; Nonlinear distortion; Solid state circuits;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1973.1050397
Filename
1050397
Link To Document