High-voltage simultaneous diffusion silicon-gate CMOS

A complementary metal-oxide-semiconductor fabrication process has been developed for low-power-consumption biomedical applications. This process realizes low gate-drain and gate-source capacitances useful for high-speed low-capacitive coupling noise circuitry, on the same integrated circuit die with high-voltage p-channel transistors capable of withstanding greater than 75V. Details of the process and device parameters and experimental correlations relating these two parameters are given. A high-voltage driver scan circuit is presented as an example of the capability of this process.